1) Field of the Invention
The present invention relates to a method of fabricating a semiconductor device, particularly, a semiconductor device that includes field effect transistors (MISFETs or MOSFETs) each of which is operable at a high speed and has a gate electrode formed of a metal silicide layer alone, and the semiconductor device.
2) Description of the Related Art
The recent microfabrication of semiconductor integrated circuit devices (hereinafter, simply referred to as “semiconductor devices”) leads to miniaturization of the electrodes of semiconductor elements. To improve the drive performance of semiconductor elements, the metal silicide is formed on the top surfaces of the gate electrode, the source region and the drain region. To reduce the contact resistance between these regions and an overlying wire, metal silicides, such as titanium silicide, cobalt silicide, or nickel silicide, are used. To form the metal silicide, sides of the gate electrode are covered with a side wall spacer, a metal layer is deposited on the substrate, and the resultant structure is subjected to a heat treatment to thereby form a metal silicide on the gate electrode, the source region, and the drain region in a self-aligned manner.
As a partly silicidized polysilicon electrode is used for the gate electrode and the microfabrication makes the gate insulating layer thinner, impurity penetration would occur at the time of ion injection of an impurity, such as boron (B). If the concentration of B is made lower to prevent the penetration of B, depletion of the gate electrode occurs. A solution to this problem has been proposed, which uses a metal gate that does not cause depletion in place of the polysilicon electrode. The use of the metal gate can decrease the resistance of the gate electrode as well as overcome the problem of depletion, thereby ensuring smaller signal delay and power reduction.
Methods of fabricating a metal gate proposed include a method of depositing metal, instead of polysilicon, by sputtering and patterning the metal into the pattern of the gate electrode, and a damascene gate processing method using CMP (Chemical Mechanical Polishing). The sputtering method similar to the fabrication process for the current polysilicon electrode except for the electrode material involves multiple problems, such as difficulty in processing the metal electrode, degradation of the characteristic of the insulating layer caused by physical damages on the top surface, and reduction in the reliability of the gate insulating layer and the gate electrode by the activation process.
In case of the damascene gage process, however, after the transistor portion that is covered with an interlayer insulating layer is planarized by CMP, the dummy gate portion is selectively removed to form a gate insulating layer. Next, a metal layer (of, for example, TiN, WN, TaN, W or the like) is formed as the gate electrode, and is planarized by CMP, thereby forming a metal electrode. When a similar metal layer is used as the gate electrode, however, the work function of the gate electrode for an n-type MOSFET becomes equal to the work function for a p-type MOSFET. In case of a polysilicon gate, for example, with B and P (Phosphorus) injected, the work function for an n-type MOSFET becomes 4.05 eV and the work function for a p-type MOSFET becomes 5.17 eV. Therefore, the use of a similar metal layer makes it very difficult to adjust the threshold voltage. This requires a dual metal gate process which uses different metal materials for an n-type MOSFET and a p-type MOSFET as a gate electrode. Adequate control of the threshold voltage requires a material having a work function of 4.1 to 4.4 eV for the n-type gate electrode and a material having a work function of 4.8 to 5.1 eV for the p-type gate electrode. The requirement should face the difficulty of selecting the proper materials and the complexity of the process.
Recently, attention has been paid to a gate electrode formed only of silicide which facilitates adjustment of the work functions of an n-type MOS transistor and a p-type MOS transistor (see non-Patent Literatures 1 to 3: B. Tavel et al, International Electronic Devices Meeting Tech. Dig., 2001, pp. 37. 5.1; W. P. Maszara et al, International Electronic Devices Meeting Tech. Dig., 2002, pp. 367; and Qi Xiang et al, VLSI Technology, 2003. Digest of Technical Papers. 2003 Symposium on, 2003, Pages: 101 to 102, respectively). When a metal silicide layer is used as a gate electrode, its work function is the mid gap of silicon, which is desirable for the gate electrode. It is known that as the work function is controllable by an impurity in the polysilicon, the work function can be controlled according to each of an n-type MOS transistor and a p-type MOS transistor. In this respect, a semiconductor device fabricated by using the damascene gate process has been proposed to form a gate electrode only of a metal silicide layer. This semiconductor device is a device with the entire gate silicidized by silicidizing the source and drain regions and a part of the gate electrode first, then depositing an interlayer insulating layer, planarizing the interlayer insulating layer by CMP to expose the top surface of the gate electrode, depositing a metal layer to be silicide, and then subjecting the resultant structure to a heat treatment, as done according to the current silicidizing technology. The reason for the double silicidization is because the silicide of the gate electrode is thicker than the silicide of the source and drain regions. Silicidizing the source and drain regions according to the thickness of the silicide of the gate electrode at the same time increases the junction leak at the source and drain regions.